ETRAX 100LX MCM 4+16 Designer's Reference

Table of content

• 1 MCM content

• 2 ETRAX 100LX MCM pinout

• 3 SDRAM configuration options

• 4 Implementation examples

  • 4.1 SDRAM implementation examples

    • 4.1 16 MByte RAM (16 bit mode), 4 MByte flash

    • 4.1 32 MByte RAM (16 bit mode), 6/8/12 MByte flash

    • 4.2 32 MByte RAM (32 bit mode), 6/8/12 MByte flash

    • 4.3 64 MByte RAM (32 bit mode), 6/8/12 MByte flash

  • 4.2 Reset implementation

  • 4.3 External Ethernet

• 5 2+8 and 4+16 compatibility

• 6 MCM mechanical drawings

• 7 PCB design recommendations

• 8 Revision History ETRAX 100LX MCM 4+16

The ETRAX 100LX MCM 4+16 is a multi chip module that contains:

#	Component	Description
1	CPU	Axis ETRAX 100LX
1	32 Mbit Flash	Atmel AT49BV322A
1	128 Mbit SDRAM	Micron MT48LC8M16A2TG-75
1	10/100 Ethernet PHY	TDK 78Q2120C
2	Reset circuit	Maxim 811S
60	Passives

Table 1

For a complete pinout description please see the ETRAX 100LX datasheet. The table below only describes the pinout differences between ETRAX 100LX, ETRAX 100LX MCM 2+8 and ETRAX 100LX MCM 4+16. The Description fields describes the functionality of ETRAX 100LX MCM 4+16.

 

Pin	MCM 2+8	MCM 4+16	ETRAX 100LX	Dir	Description
Ethernet / Phy
U20	phyen_	phyen_	VCC	in	Active low. A low signal level on this input enables the internal Ethernet transceiver. A high signal level will put the internal Ethernet transceiver in isolate mode and this will put all MII outputs of the transceiver in 3-state. Do not leave this input unconnected.
W18	rx+	rx+	NC	in	Receive pair. Differential data from the media is received on the rx+/- signal pair.
V18	rx-	rx-	NC	in
Y20	tx+	tx+	NC	out	Transmit pair. Differential data from the media is transmitted on the tx+/- signal pair.
W19	tx-	tx-	NC	out
V2	phybias	NC	NC	-	Leave unconnected.
W10	NC	phyrst_	hcfg	in	This signal controls the reset signal to the internal Ethernet transceiver. This signal should normally be connected directly to the reset_ output (Y10). Do not leave this input unconnected.
SDRAM Configuration
C16	conf0	conf0	NC	in	These pins decide how the internal SDRAM shall be configured. Either it is configured in 16-bit mode or in 32-bit mode. Please see SDRAM configuration options for further details.
B17	conf1	conf1	NC	in
A19	conf2	conf2	NC	in
B18	conf3	conf3	NC	in
D16	conf4	conf4	NC	in
V10	NC	sdramen	pllvss	in	This input enables/disables the internal SDRAM. If external SDRAM is used in same address area as the internal SDRAM the internal SDRAM must be disabled. Connect to GND if you whish to disable the internal SDRAM. Signal has an internal pull up.
SDRAM Interface
C5	csd0_	csd0_	ras0_	out	These pins have exactly the same functionality as documented in ETRAX 100LX Designer's Reference.
B4	csd1_	csd1_	ras1_	out
A3	sdramclk	sdramclk	ras2_	out
D5	cke	cke	ras3_	out
E4	dqm0	dqm0	casa0_	out
C1	dqm1	dqm1	casa1_	out
D1	dqm2	dqm2	casa2_	out
E2	dqm3	dqm3	casa3_	out
F3	dqm4	dqm4	casb0_	out
G4	dqm5	dqm5	casb1_	out
F2	dqm6	dqm6	casb2_	out
F1	dqm7	dqm7	casb3_	out
G3	dqs	dqs	dramwe_	out
Reset
B3	mreset_	mreset_	NC	in	Active low master reset input for the ETRAX 100LX MCM. This signal needs so be asserted for a minimum of 10us for the reset to have effect.
Y10	reset_	reset_	reset_	out	Reset output. This reset signal is used for making a reset of the internal ETRAX 100LX and flash chip. The same signal can be used for making a reset of external circuits as well. The reset output will remain asserted as long as mreset_ is low and for 180ms after mreset_ turns high. This signal is normally tied to the phyrst_ (W10) input.
Other
A16	NC	NC	testout	out	Signal pins on ETRAX 100LX but NOT on ETRAX 100LX MCM.
U18	NC	NC	testout2	out
Y9	NC	NC	plllp2	out
W9	NC	NC	pllagn	out

Table 2

The internal SDRAM is a 2M x 4 banks x 16 bit. This internal chip lies in group 0 (CSD0_). If 16-bit mode is selected, no extra memory is needed but it can optionally be added in group 1 (CSD1_). If 32-bit mode is selected you need to add an additional SDRAM chip on data bit 16-31 in group 0. This chip must be 2M x 4 banks x 16 bit. It is important to point out that if both SDRAM groups are used, the chip configuration of the two groups must be the same. The ETRAX 100LX MCM 4+16 can have a total amount of 128 MByte RAM if the internal RAM is used.

16 or 32 bit configuration is selected by connecting different address signals to the conf 0-4 pins as shown below.

	16 bit	32/64 bit
conf0	A01	A10
conf1	A10	A11
conf2	A11	A12
conf3	A12	A13
conf4	A13	A15

Table 3

The examples below describes how additional units, e.g. external memory, can be connected to the ETRAX 100LX MCM 4+16.

4.1 SDRAM implementation examples

Flash: Always 16 bit mode. Address area 0x00000000-0x03FFFFFF (CSE0_) occupied by internal 4 MByte flash. The examples show how to add more flash memory externally. Larger flash chips than 8 Mbyte can be used, even though this is not shown in the examples. Larger flash memories requires more address lines.

SDRAM: Configurable 16/32/64(WMM) bit mode. 16 MByte SDRAM internally located in group0, using DQM0 and DQM1.

4.1.1 16 MByte RAM (16 bit mode), 4 MByte flash

This implementation has a total flash amount of 4 MByte and 16 MByte SDRAM, and thus no external memory chips. Both the Flash and RAM is configured with 16 bit bus width. The address feedback to the conf0-4 inputs must be according to 16 bit mode in table 3.

R_SDRAM_CONFIG: 0x09603636
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

4.1.2 32 MByte RAM (16 bit mode), 6/8/12 MByte flash

This implementation has a total flash amount of 6, 8 or 12 MByte and 32 MByte SDRAM. Both the Flash and RAM is configured with 16 bit bus width. The address feedback to the conf0-4 inputs must be according to 16 bit mode in table 3.

R_SDRAM_CONFIG: 0x09783636
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

NOTE: The configuration of the internal SDRAM causes limitations on how the address pins of the external SDRAM can be connected. Below is a recommendation on how to connect the address pins of the external SDRAM.

MCM pin	SDRAM pin
A1	A8
A2	A0
A3	A1
A4	A2
A5	A3
A6	A4
A7	A5
A8	A6
A9	A7
A10	A9
A11	A10
A12	A11

4.1.3 32 MByte RAM (32 bit mode), 6/8/12 MByte flash

This implementation has a total flash amount of 6, 8 or 12 MByte and 32 MByte SDRAM. The Flash is configured with 16 bit bus width and the RAM with 32 bit bus width. The address feedback to the conf0-4 inputs must be according to 32 bit mode in table 3.

R_SDRAM_CONFIG: 0x09e05757
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

4.1.4 64 MByte RAM (32 bit mode), 6/8/12 MByte flash

This implementation has a total flash amount of 6, 8 or 12 MByte and 64 MByte SDRAM. The Flash is configured with 16 bit bus width and the RAM with 32 bit bus width. The address feedback to the conf0-4 inputs must be according to 32 bit mode in table 3.

R_SDRAM_CONFIG: 0x09f95757
R_SDRAM_TIMING: 0x80008002^*

Chip configuration	SDRAM group configuration

* R_SDRAM_TIMING is adjusted to the timing demands of the internal SDRAM. For a complete description of the registers we refer to ETRAX 100LX register definitions

4.2 Reset implementation

The ETRAX 100LX MCM 4+16 contains a reset circuit that takes care of the internal reset. Thus an external reset circuit is not necessary for proper functionality but can be added if the product implementation requires it. The mreset_ input controls the internal reset circuit and can be connected as the picture shows. The reset_ output from the MCM is the same signal that makes a reset of all internal circuits, and can be used to reset external peripherals such as memory etc. The mreset_ input is active low and can be left unconnected if unused.

4.3 External Ethernet transceiver

It is possible to connect external Ethernet transceivers to the MCM module. Please note that the ETRAX 100LX MCM 4+16 has only one Ethernet MAC controller. The MII interface supports multiple Ethernet transceivers connected to the same bus, only one Ethernet transceiver can be active at one time. All Ethernet transceivers must have a unique address, this is normally configured by connecting pull up/down resistors to the address inputs of the transceiver. The internal Ethernet transceiver uses address 1.
There is a control signal on the ETRAX 100LX MCM 4+16 called phy_enable_ which can be used to enable/disable the internal Ethernet transceiver. A logic zero will enable and a logic one will disable the internal transceiver.
It's important to point out that this is a feature which is normally not used. It's more of a clarification of the MII standard than a special feature of the MCM module.

The purpose of this section is to describe changes that has to be done in order to support both ETRAX 100LX MCM 2+8 and ETRAX 100LX MCM 4+16. In this implementation example both 2+8 and 4+16 are supported and can be used as a reference.

Pin	ETRAX 100LX MCM 2+8		ETRAX 100LX MCM 4+16
Ethernet / Phy
V2	phybias	Connect decoupling capacitors to ground.	NC	Optionally connect. Signal is not connected to internal devices.
SDRAM Configuration
C16	conf0	Connect according to ETRAX 100LX MCM 2+8 Designer's Reference	conf0	Connect according to Table 3.
B17	conf1		conf1
A19	conf2		conf2
B18	conf3		conf3
D16	conf4		conf4
Other
W10	NC	Optionally connect. Signals are not connected to internal devices.	phyrst_	Connect according to Table 2.
V10	NC		sdramen

Table 4

See the mechanical drawings for full info about footprint, etc.

Common design rules should be applied. Pay special attention to high frequency traces. They should be as short as possible and preferably close to a ground layer. TX+/- and RX+/- traces from the Ethernet transceiver should have the same length and be routed adjacent to a GND layer. The differential impedance should be 100 ohm. Have a look at an implementation example of how to use the ETRAX 100LX MCM in a design for further information.